The present invention relates to a logic circuit of MOS transistors and, more particularly, to a logic circuit having a voltage booster.
Conventionally, a logic circuit having a voltage booster in an output stage thereof has been adopted to improve the efficiency of data transfer and to decrease power consumption in the field of semiconductor memories such as a RAM (random access memory) which allows data read/write operations and a ROM (read-only memory) which allows only data read operations. In the logic circuit of the type described above, an output buffer at the output stage of the logic circuit comprises an enhancement-type MOS transistor. A switching input signal to be supplied to the gate of this MOS transistor is boosted by a voltage booster arranged at the same output stage. The boosted voltage is then supplied to the gate of the MOS transistor so as to keep a voltage level of an output signal of logic level "1" from the output buffer coincident with the power source voltage level. However, in a conventional logic circuit, no means is provided to stably maintain the boosted voltage obtained from the voltage booster. A leakage current occurs at a p-n junction connected to the output end of the voltage booster. The boosted voltage becomes equal to or lower than the power source voltage over a predetermined period of time.
FIGS. 1A to 1C, respectively, show conventional circuits of the type described above. FIG. 1A shows a general logic circuit for boosting an input signal so as to obtain a boosted output signal. In this circuit, a decoder output signal or a predetermined logic signal is supplied to an input end (signal input end) A of an input buffer circuit 11. An output signal appearing at the output end B of the input buffer circuit 11 is supplied to a series circuit of inverters 12 and 13 and a capacitor 14. When the signal at the input end A goes from logic level "0" to logic level "1", a signal which becomes high appears at the output end B of the input buffer circuit 11. The output signal of logic level "1" is delayed by the inverters 12 and 13 (i.e., the signal of logic level "1" is inverted twice). The inverter 13 then generates an output signal of logic level "1", and this signal of logic level "1" is boosted through the capacitor 14 and appears at the output end B. The boosted voltage signal appearing at the output end B is supplied to the gate of a switching transistor (i.e., a row line of a semiconductor memory).
FIG. 1B shows another conventional circuit. This circuit comprises a delay circuit 20 and a voltage booster 30. The delay circuit 20 comprises n-channel (all transistors referred to hereinafter are of n-channel type) MOS transistors 21 to 24. A series circuit of the MOS transistors 21 and 22 is connected between a positive power source voltage VC and the ground potential. A series circuit of the MOS transistors 23 and 24 is also connected between the positive power source voltage VC and the ground potential. A node C of the MOS transistors 21 and 22 is connected to the gate of the MOS transistor 24. An input signal .phi.l is supplied to the gate of the MOS transistor 21. A signal .phi.p is supplied to the gates of the MOS transistors 22 and 23. A node between the MOS transistors 23 and 24 corresponds to an end D.
The voltage booster 30 comprises five MOS transistors 31 to 35 and a capacitor 36. A series circuit of the MOS transistors 31 and 32 is connected between a signal (.phi.l) applying point and the ground potential. The MOS transistor 33 is connected between the end D and an end E connected to the gate of the MOS transistor 31. A series circuit of the MOS transistors 34 and 35 is connected between a power source voltage VC and the ground potential. The capacitor 36 is connected between a node F of the MOS transistors 34 and 35 and the gate of the MOS transistor 34. A node G of the series circuit of the MOS transistors 31 and 32 is connected to the gate of the MOS transistor 34. The end D is connected to the gate of the transistor 35. A signal .phi.p is supplied to the gate of the MOS transistor 32. The power source voltage VC is applied to the gate of the MOS transistor 33. In this circuit, when the signals .phi.p and .phi.l are set to logic levels "1" and "0", respectively, the ends C, D, and E and the nodes F and G are set to logic levels "0", "1", "1", "0" and "0", respectively. When the input signal .phi.l becomes logic level "1" after the signal .phi.p becomes logic level "0", the node G is set to logic level "1" in response to the input signal .phi.l through the MOS transistor 31. In this condition, since the end D is kept at logic level "1", the node F is kept at logic level "0". The signal .phi.l is delayed by the delay circuit 20 and is supplied through the end D, so that the end D becomes logic level "0". The end E becomes logic level "0" through the MOS transistor 33. Then, the MOS transistor 31 is turned off. At the same time the MOS transistor 35 is turned off. The node F is then set to logic level "1". A voltage appearing at the node G is boosted by the capacitor 36.
FIG. 1C shows still another conventional circuit 40. The circuit 40 is frequently coupled to a decoder or the like and comprises four enhancement-type MOS transistors 41 to 44, a depletion-type MOS transistor 45 and a capacitor 46. The MOS transistor 41 is connected between ends I and J. The end I receives an output signal from a decoder 50. A series circuit of the MOS transistors 45 and 42 is connected between a positive power source voltage VC and the ground potential. The gate of the MOS transistor 45 used as a load element is connected to a node K between the MOS transistors 45 and 42. The gate of the MOS transistor 42 is connected to the end I. A series circuit of the MOS transistors 43 and 44 is connected between the power source voltage VC and the ground potential. The gate of the MOS transistor 43 is connected to the end J. The gate of the MOS transistor 44 is connected to the node K. The capacitor 46 is connected between a node L of the MOS transistors 43 and 44 and the gate of the MOS transistor 43. In this circuit, an E/D inverter 47 is constituted by the enhancement-type MOS transistor 42 and the depletion-type MOS transistor 45. When the signal at the end I from the decoder 50 becomes logic level "1", a signal of logic level "1" is supplied to the end J through the MOS transistor 41. In this condition, however, the node K is kept at logic level "1", the MOS transistor 44 is turned on, and the end L is still kept at logic level "0" . When the signal of logic level "1" is then delayed and inverted by the inverter 47 (i.e., the node K becomes logic level "0"), the end L is set to logic level "1". A voltage signal at the end J is boosted by the capacitor 46. In this condition, the MOS transistor 41 is turned off. Thereafter, the MOS transistor 43 is operated in the same manner as that of a triode, and a voltage corresponding to the power source voltage VC appears at the end L. The end L is connected to a row line of a semiconductor memory (not shown).
In the circuits shown in FIGS. 1A to 1C, however, boosted voltages appearing at the ends B, G and J, respectively, decrease over a predetermined period of time due to leakage currents at the p-n junctions equivalently connected to the voltage booster. The boosted voltages obtained cannot then be used for proper operation, which is highly inconvenient.